ASIX Home

SIGMA2 vs. OMEGA

 
: Mapa stránek : Home > Produkty > Ladicí prostředky > Srovnání SIGMA2 a OMEGA 2018-02-21

 

Home Produkty

Programátory

PRESTO FORTE

Logické analyzátory

SIGMA2 OMEGA

USB produkty

UCAB232 UCAB232i

Ostatní produkty Integrované obvody Muzeum

Vývoj s výrobou Obchod & ceny Podpora ASIX s.r.o. Kontakt



Srovnání logických analyzátorů SIGMA2 a OMEGA


Parameter SIGMA2 OMEGA
Standard mode
(with advanced trigger logic)
16 inputs / 50 MSPS 16 inputs / 200 MSPS
Accelerated mode
(with simple triggering)
◊ 8 inputs / 100 MSPS
◊ 4 inputs / 200 MSPS
8 inputs / 400 MSPS
PC interface USB 2.0 Full Speed (12 Mbps)
powered from USB, no external supply required
USB 2.0 High Speed (480 Mbps)
powered from USB, no external supply required
Sample memory size
Maximal test length - each successive sample differs (data cannot be compressed).
14.7 million 29.8 million
Typical number of samples
Tested with I2C, SPI or UART serial protocols.
2 millions input signal changes 20 to 30 millions input signal changes
Max. test length /
max. test time

Test length / time with no signal changes on the inputs.
128 G / 45 min. 862 G / 77 min.
Worst condition test length 0.29 s 0.15 s
Maximum compressed data flow 915 Mbps 3.6 Gbps
Synchronization N/A ◊ 2 analyzers (up to 32 inputs): ±5 ns
◊ 3 analyzers (up to 48 inputs): ±10 ns
◊ more: possible but without timing specification
On the market Since 2011
(SIGMA since 2007)
Since 2012
Price
(end user, for 1 unit, w/o VAT)
4 800 Kč 7 000 Kč


Technické detaily


Parameter SIGMA2 OMEGA
Number of inputs 16
Input logic level TTL
Input buffers 74LVC245, TSSOP
ESD protection 27 Ohm serial input resistor + built-in CMOS ESD protection
Trigger conditions
in standard mode
Advanced, 3 masks
Resolution: 1 sample (20 ns)
Advanced, 3 masks
Resolution: 2 samples (10 ns)
FPGA Xilinx Spartan-3 Xilinx Spartan-3A
Memory SDRAM, 256 Mbit, 16-bit bus, ~66 MHz SDRAM, 512 Mbit, 32-bit bus, ~133 MHz
Compression method RLE RLE + Huffman coding
Maximum RLE run count 64 K 32 K
External Trigger-In LVTTL (max. 3.3 V)
External Trigger-Out LVCMOS (3.3 V) with 1 kOhm serial resistor
or open collector with pull-up
LVCMOS (3.3 V)
Auxiliary power output On Trigger-In pin, 2.7 to 3.3 V, max. 100 mA
Target cables CAB20LA (colored wires with individual numbered sockets)
CAB2020 (20-pin header for 16 channels)
CAB2010 (10-pin header for 8 and 4 channels)
CAB20LA (colored wires with individual numbered sockets)
CAB2020 (20-pin header for 16 channels)
CAB2010 (10-pin header for 8 channels)
Synchronization cable
User interface 2 LEDs (green/yellow and red/yellow)
GO button (test ➜ trigger ➜ stop)
Software All-in-one package: Logic analyzer + utilities +USB Driver + documentation
Protocol analyzers Free: UART, SPI, I2C
Optional: USB Full Speed (12 Mbps)



Máte-li zájem o další informace, zeptejte se nás.

© ASIX s.r.o., 1991- 2018. All rights reserved.